The present invention relates generally to computer systems and, more particularly, to methods and apparatus for structuring multiple processor computer systems to provide for the interconnection of multiple processors to multiple system buses and to multiple I/O subsystem buses. The I/O subsystem buses are interfaced to the system buses for buffering data to be written to or read from the memory by agents resident on the I/O subsystem buses, and all system buses and I/O subsystem buses are independently arbitrated to define a decoupled bus system for the multiple processor computer systems.
Computer systems have traditionally included a central processing unit or CPU, data storage devices including a main memory which is used by the CPU for performance of its operations and a system bus which interconnects the CPU to the main memory and any other data storage devices. In addition, I/O devices are connected to the system via the bus. The bus thus serves as a communications link among the various devices making up a system by carrying clock and other command signals and data signals among the devices.
As processors and memory devices evolve, computer systems are being operated at higher and higher speeds to transmit more and more data and command signals in less time over a system bus. To alleviate some of the communications burdens, computer systems which include multiple buses have been developed. For example, a high speed bus may be provided to interconnect a processor to associated high speed memory and a slower speed I/O bus to interconnect to slower input/output devices. Multiple bus computer systems can carry higher volumes of data and control signals; however, multiple bus computer systems create their own control challenges in terms of control of the multiple buses.
To attain still higher speeds, multiple processor systems have also been developed. Of course the number of control and data signals required for operation of multiple processor systems are greater than those required for single processor systems. It is apparent that the complexity of communications among units within a computer system is further increased by multiple processor systems. The complexity of communications within multiple processor systems is still further increased when such systems incorporate multiple buses.
While the use of conventional techniques, such as organizing and programming multiple processor systems to minimize interactions among the processors, can improve the operations of existing computer system architectures, there is a continuing need for new and improved computer system architectures to advance the art and to provide better operating computer systems. Such an improved system architecture would preferably be scalable to provide a wide variety of system configurations for a correspondingly wide variety of applications. In this way, a computer system could be configured for a given application and expanded and contracted in accordance with development of the application within limits of the preliminary configuration.